The SIP (System in package) technology with which a plurality of semiconductor chips are stacked in three dimensional directions (in the direction of height) to be integrated in one package has been developed. FIGS. 5 and 6 are drawings showing an example of a structure of such semiconductor device of prior art. FIG. 5 shows a cross sectional view and FIG. 6 shows a plan view seen from the above. In this example, a second chip 20 is stacked on a first chip 10, and a memory (DRAM) 11 and others are included in the first chip 10 as an integrated circuit and a CPU (Central Processing Unit) Block 21 and others are included in the second chip 20 as an integrated circuit. Further, the first chip 10 is made to be somewhat larger than the second chip 20.
The memory 11 in the first chip 10 is formed of a plurality of DRAMs; a selector 12 is provided to select from the plurality of DRAMs; and the memory 11 is connected to the CPU block 21 on the second chip 20 side through the selector 12. A selector is also provided on the CPU block 21 side. The details with respect to the structure connected through these selectors are described later; each selector also has a register function that retains data temporarily.
As the structure for connecting the memory 11 and the CPU block 21, as shown in FIG. 6, a pad 13aconnected to the selector 12 with the internal wiring is provided on the first chip 10 side and a pad 22aconnected to the CPU block 21 with the internal wiring is provided on the second chip 20 side. Then, the pad 13a on the first chip 10 side and the pad 22a on the second chip 20 side are connected with a wire 31 such as a copper wire. Although only one set of the pads 13a, 22a and wire 31 is shown in FIG. 6 to make the explanation simplified, a plurality of those sets are arranged in actuality, in which parallel data can be transferred.
A predetermined number of pads 22b connected to the CPU block 21 with the internal wiring are provided on the second chip 20 side in order to connect the CPU block 21 to the outside. A predetermined number of pads 13b are provided on the first chip 10 side at a position adjacent to each of pads 22b, and further a predetermined number of pads 13cconnected to the pad 13b with the internal wiring are provided in the peripheral portion of the first chip 10. Then, the pads 22b on the second chip 20 side and the pads 13b on the first chip 10 side are connected with the wire 31, and the pads 13cin the peripheral portion of the first chip 10 are connected to the electrode on the package side (not shown in the figure) with the wire 32.
Hereupon, FIG. 7 shows an example of a state of prior art in which the CPU block 21 on the second chip 20 side and the memory 11 on the first chip 10 side are connected. In the example of FIG. 7, four DRAMs 11a, 11b, 11c and 11d constitute the memory 11, and each of DRAMs 11a to 11d is connected to the register and selector 12 through the internal wiring in the chip 10. The selector 12 is connected to the register and selector 21a on the CPU block 21 side through the wire 31 connecting the chip 10 and chip 20, and the register and selector 21a is connected to the circuit in the CPU block 21 through the internal wiring.
As shown in FIG. 7, the CPU block 21 side and the DRAMs 11a to 11d side are connected through the registers and selectors 12, 21a, to perform selectively the readout from or writing to the four DRAMs 11a to 11d, and further the readout or writing is performed dividedly in one selected DRAM. For example, in the case where data of originally 128 bits is read or written in parallel in one DRAM, both the selectors 12 and 21a are connected with thirty-two wires, and the readout or writing of 128 bits data is performed four times dividedly.
The above described structure in which a plurality of semiconductor chips are stacked is disclosed in Published Japanese Patent Application No. H8-167703 issued by Japanese Patent Office.
Here, in the structure shown in FIGS. 5 through 7, the CPU block on the first chip 10 and the memory on the second chip 20 are connected through the register and selector, so that the number of the wires 31 (and pads connected to the wires) connecting both the chips 10, 20 is made to be comparatively small and consequently wires connecting two chip components are reduced. If the number of wires increases, it takes time to connect chip components, which is unfavorable. Further, because there is a limit regarding the area on the chip where pads can physically be arranged, the number that can be connected is also restricted.
However, when the writing and readout are dividedly performed with the connection through the selector as described above, there is a problem that it takes time to access the memory. Although it is necessary to increase the transfer rate of data in order to shorten the time required for the access, there are such problems that the distortion is easily caused with respect to the waveform at the high transfer rate due to a large inductance component of the wire portion in the case where the connection was made with the wires and that the undesirable radiation and the power consumption may increase.
Further, in the case where two chips are stacked and connected as described above, only in order to connect the circuit block in one chip to an electrode on the package side, the chip is required to be connected to the other chip component with the wire, and so there is a problem that the connected structure becomes complicated. Specifically, for example, in the example of FIGS. 5 and 6, in order to connect the CPU block 21 on the second chip 20 side to the electrode on the package side, the connection is made to the internal wiring on the first chip 10 side with the pad 22b, wire 31 and pad 13b, and further the connection is made from the pad 13c in the peripheral portion of the first chip 10 to the electrode on the package side with the wire, and so the connected structure becomes complicated. Further, when the wire (part of the wire 31) to connect the CPU block 21 and the electrode on the package side and the wire (part of the wire 31) to connect the CPU block 21 and the memory are arranged adjacently to each other, the influence of the above described undesired radiation is mutually received, which is not preferable in view of characteristics thereof.
The present invention is to provide a semiconductor device in which the connected structure can be simplified and favorable characteristics can be obtained in the case of stacking a plurality of semiconductor chips.